1. Field of the Invention
This invention relates to improvements in interface circuitry for passing a digital data word from one system to another, and more particularly to improvements in interface circuitry for passing a digital data word in half-word portions from a system under control of a controller, or the like, to a read channel of a mass data storage device, or the like, for writing to a data storage medium thereof in synchronism with a clock signal internal to the read channel.
2. Relevant Background
In mass data storage devices, typically data is read from a data storage device, such as a hard disk drive, or the like, on which it is stored. The data is processed in a read channel, in which various data recognition, modification, and filtering processes are preformed, after which, the data is delivered to a controller for use in an associated computer or other system. Conversely, when data is to be written to the data medium, it is delivered under the control of the controller to the read channel, which performs other data modification processes to the data, and the data is delivered to the data transducers or heads to be written onto the data medium.
Typically, an interface circuit is provided between the read channel and the controller to receive data to be written to the storage medium via the read channel. In this process, data is typically sent in packets. Between packets, however, the controller causes data values of only zero to be transmitted to the read channel. When the data transmission is first initiated, a non-zero word is transmitted to the read channel for detection by the read channel to enable the necessary data receiving signals and mechanisms to be set up to receive the succeeding data words.
The interface for the read channel to the controller is essentially asynchronous, since the read channel device has no a priori knowledge of when the data will be transferred. The read channel device generates the clock for the external controller device so it can synchronize data sent to it via the interface. The external controller is generally much slower than the read channel device, so it cannot respond as fast as the read channel device.
Also, in the past, interface circuits of the type described typically are individually or custom designed for each particular application in which they are used. One of the reasons for this is that some systems transfer data in complete word formats, whereas others transmit data in half-word nibbles, which requires different circuitry and signal processing from the entire word. This is primarily done to reduce the number of pins required to transfer data.
The tradeoff, however, is that the data transferred in half-word nibbles needs to be sent by the controller at twice the speed of the full word transfer.
What is needed therefore is an interface circuit that is portable among different configurations so that it can be easily configured to transfer either whole or half-word portions of the signal being processed.
One of the distinctions of this circuits and the prior art is that this circuit provides a clock that is sent to a controller or microprocessor, and the controller or microprocessor synchronizes the data transmitted to the interface circuit based upon the clock provided by the interface circuit.
It is therefore an advantage of the invention to be enabled to provide an interface circuit that can be easily selectively configured to receive data in either full or half-word portions.
It is another advantage of the invention to be enabled to provide an interface circuit that can receive data in portions, for example half-word portions, that is portable and easily configurable between chip designs.
In light of the above, therefore, according to a broad aspect of the invention, an interface circuit is provided to interface data that is transmitted in either full or half-word portions from a controller to a data user. In the half-word mode, a first half-word data input register receives a data word in sequential half-word portions. The first half-word data input register is clocked by a first clock signal. At least second and third data registers, each clocked by the first clock signal, are connected to sequentially receive the portions of the data word from the first data register to form a data pipeline. First and second data output registers, each clocked by a second clock signal at a frequency half that of the first clock signal, deliver data therein to the data user. First and second multiplexers having outputs are respectively connected to the first and second data output registers. Each has outputs selected from the first, second, and third registers connected to inputs thereof. A controller controls the multiplexers to pass selected outputs from the first, second, and third registers. The controller determines in which of the three registers the data word portions are contained, based upon the relative phase of the first and second clock signals with respect to the time that the data word was received.
According to another broad aspect of the invention, a half-word synchronous interface circuit is provided to interface a data word that is transmitted in half-word portions from a controller to a data user. The circuit includes a first half-word data input register for receiving a data word in sequential half-word portions, clocked by a first clock signal. At least second and third data registers, each clocked by the first clock signal, are connected to sequentially receive the portions of the data word from the first data register. First and second data output registers, each clocked by a second clock signal at a frequency half that of the first clock signal, deliver data therein to the data user. First and second multiplexers have outputs respectively connected to the first and second data output registers, and each having outputs from the first, second, and third registers connected to inputs thereof. A controller controls the multiplexers to pass selected outputs from the first, second, and third registers. The controller is operative to determine in which of the three registers the data word portions are contained, based upon the relative phase of the first and second clock signals with respect to the time that the data word was received.
According to yet another broad aspect of the invention, a method for interfacing a data word that is transmitted in half-word portions from a controller to a data user is provided. The method includes providing clock signals to control a transfer of the data at a first and second clock frequencies, the first clock frequency being half the second clock frequency. The method also includes determining whether the first and second clock frequencies are in-phase or out-of-phase when first and second half-word portions of a data word are received. The method also includes selectively and concurrently outputting the half-word portions of the data word in a proper order depending upon whether the first and second clock frequencies were determined to be in-phase or out-of-phase. In one embodiment, the method includes clocking first and second nibbles of the data word into respective first and second registers, or second and third registers depending upon whether the first and second clock frequencies are in-phase or out-of-phase for selective output therefrom.